Field Programmable Analog Array Research Articles

Field-Programmable Analog Array Implementation of Neuromorphic Silicon Neurons with Fractional Dynamics

Silicon neurons are bioinspired circuits with the capability to reproduce the modulation through pulse-frequency observed in real neurons. They are of particular interest in closed-loop schemes to encode the control signal into pulses. This paper proposes the analog realization of neuromorphic silicon neurons with fractional dynamics. In particular, the fractional-order (FO) operator is introduced into classical neurons with the intention of reproducing the adaptation that has been observed experimentally in real neurons, which is the variation in the firing frequency even when considering a constant or periodic incoming stimulus. For validation purposes, simulations using a field-programmable analog array (FPAA) are performed to verify the behavior of the circuits.

Elementary Negative Group Delay Filter Functions

AbstractA theoretical study of the behavior of some elementary first- and second-order functions, which are suitable for realizing negative group delay, is performed in this work. As both the gain and phase responses are simultaneously considered, important derivations related to the actual bandwidth of operation are derived accompanied by useful design tips. The presented theory is supported by simulation and experimental results obtained through the utilization of typical active-RC filter structures, as well as from a field-programmable analog array device.

Extrema-Triggered Conversion for Non-Stationary Signal Acquisition in Wireless Sensor Nodes

While wireless sensor node (WSNs) have proliferated with the rise of the Internet of Things (IoT), uniformly sampled analog–digital converters (ADCs) have traditionally reigned paramount in the signal processing pipeline. The large volume of data generated by uniformly sampled ADCs while capturing most real-world signals, which are highly non-stationary and sparse in information content, considerably strains the power budget of WSNs during data transmission. Given the pressing need for intelligent sampling, this work proposes an extrema pulse generator devised to trigger ADCs at significant signal extrema, thereby curbing the volume of data points collected and transmitted, and mitigating transmission power draw. After providing a comprehensive signal-theoretic rationale, we construct and experimentally validate these circuits on a system-on-chip field-programmable analog array in a 350 nm complementary metal-oxide-semiconductor (MOS) process. Operating within a power range of 4.3–12.3 µW (contingent on the input bandwidth requirements), the extrema pulse generator has proven to be capable of effectively sampling both synthetic and natural signals, achieving significant reductions in data volume and signal reconstruction error. Using a nonideality-resilient reconstruction algorithm, that we develop in this work, experimental comparisons between extrema and uniform sampling show that extrema sampling achieves an 18-fold lower normalized root mean square reconstruction error for a quadratic chirp signal, despite requiring 5-fold fewer sample points. Similar improvements in both the reconstruction error and effective sampling rate objectives are found experimentally for an electrocardiogram signal. Using both theoretical and experimental methods, this work demonstrates the potential of extrema-triggered systems for extending Pareto frontiers in modern, resource-constrained sensing scenarios.

A Study on Fractional Power-Law Applications and Approximations

The frequency response of the fractional-order power-law filter can be approximated by different techniques, which eventually affect the expected performance. Fractional-order control systems introduce many benefits for applications like compensators to achieve robust frequency and additional degrees of freedom in the tuning process. This paper is a comparative study of five of these approximation techniques. The comparison focuses on their magnitude error, phase error, and implementation complexity. The techniques under study are the Carlson, continued fraction expansion (CFE), Padé, Charef, and MATLAB curve-fitting tool approximations. Based on this comparison, the recommended approximation techniques are the curve-fitting MATLAB tool and the continued fraction expansion (CFE). As an application, a low-pass power-law filter is realized on a field-programmable analog array (FPAA) using two techniques, namely the curve-fitting tool and the CFE. The experiment aligns with and validates the numerical results.

Real-time neural identification using a recurrent wavelet first-order neural network of a chaotic system implemented in an FPAA

Recurrent neural networks use sequential or time series data. These algorithms can be used in temporal or ordinal tasks, such as speech recognition, image captioning, and forecasting, among many others. This study introduces a novel approach to the real-time identification of chaotic trajectories using a Recurrent Wavelet First-Order Artificial Neural Network (RWFONN) in conjunction with a Field-Programmable Analog Array (FPAA). The FPAA physically implements the chaotic dynamics of a third-order Jerky equation system with reconfigurable analog electronic components through its voltage output. The trajectory acquisition of the voltage signals is carried out by a dSPACE 1104 board connected to MATLAB & Simulink and Control Desk, which serves as real-time identification data for the RWFONN. The first-order artificial network implements a Morlet wavelet activation function for the online training. It has the particularity to work without the need for multiple epoch training, validation, or dividing the data into batches. Instead, it validates the process by the filtered and mean square errors, affirming the RWFONN’s precision in identifying and reproducing the chaotic behavior of the FPAA-modeled system. This breakthrough in real-time identification holds promise for applications demanding dynamic and unpredictable behaviors, such as random number generators, neural controllers, and cryptographic systems.

ACCELERATING HIGH-PERFORMANCE VOLTAGE SOURCE INVERTER PROTOTYPING WITH FPGA IMPLEMENTATION

This paper highlights the advantages of FPGA-based rapid prototyping as a powerful tool for accelerating the development cycle of high-performance Voltage Source Inverters. By providing a flexible and efficient platform for algorithm testing, hardware evaluation, and performance optimization, it contributes to advancements in power electronics and facilitates the deployment of robust VSIs in diverse application domains. Through extensive experimentation, we demonstrate the effectiveness of the FPGA-based rapid prototyping platform in achieving high- performance VSI control. The FPGA's real-time capabilities facilitate swift algorithm development and testing, ensuring robustness and reliability. Moreover, the platform supports real-time hardware-level fault analysis and mitigation strategies, enhancing the overall resilience of the VSI. This paper presents an innovative approach utilizing Field- Programmable Gate Arrays (FPGAs) for rapid prototyping of high-performance VSIs. This abstract outlines the core objectives, methods, and potential contributions of a project aimed at expediting the development of high-performance Voltage Source Invertersthrough FPGA-based prototyping. KEYWORDS FPGA (Field-Programmable Gate Array), Voltage Source Inverter, High-Performance Prototyping, Power Electronics, Hardware-in-the-Loop (HIL), Rapid Prototyping, Real-Time Simulation, Control Algorithms, Digital Signal Processing (DSP),Power Conversion, Description Language (HDL),System-on-Chip (SoC),Field-Programmable Analog Array (FPAA),Power Quality, Grid Integration

Programmable mixed-signal circuits

A novel concept for programmable mixed-signal circuits is presented based on programmable transmission gates. For implementation, memristively switching devices are suggested as the most promising candidates for realization of fast and small-footprint signal routing switches with small resistance and capacity. As a proof-of-concept, LT Spice simulations of digital and analogue example circuits implemented by the new concept are demonstrated. It is discussed how important design parameters can be tuned in the circuity. Compared to competing technologies such as Field Programmable Analogue Arrays or Application-Specific Integrated Circuits, the presented concept allows for development of ultra-flexible, reconfigurable, and cheap embedded mixed-signal circuits for applications where only limited space is available or high bandwidth is required.

Implementation of Various Chaotic Spiking Oscillators Based on Field Programmable Analog Array

In this paper, a circuit based on a field programmable analog array (FPAA) is proposed for three types of chaotic spiking oscillator (CSO). The input/output conversion characteristics of a specific element in the FPAA can be defined by the user. By selecting the proper characteristics, three types of CSO are realized without changing the structure of the circuit itself. Chaotic attractors are observed in a hardware experiment. It is confirmed that the dynamics of the CSOs are consistent with numerical simulations.

Analog System High-Level Synthesis for Energy-Efficient Reconfigurable Computing

The design of analog computing systems requires significant human resources and domain expertise due to the lack of automation tools to enable these highly energy-efficient, high-performance computing nodes. This work presents the first automated tool flow from a high-level representation to a reconfigurable physical device. This tool begins with a high-level algorithmic description, utilizing either our custom Python framework or the XCOS GUI, to compile and optimize computations for integration into an Integrated Circuit (IC) design or a Field Programmable Analog Array (FPAA). An energy-efficient embedded speech classifier benchmark illustrates the tool demonstration, automatically generating GDSII layout or FPAA switch list targeting.

A New Nonlinear Ion Drift Model of Memristor Element and its Versatile Analog Reconfigurable Realizations

While using polynomial functions to define window functions is an initial approach in studying the memristor element, it is susceptible to generating imaginary results. However, using window functions, including the trigonometric function, is a current field of research on the memristor element. This paper uses the trigonometric Blackman window function to present a new memristor element model and investigates its nonlinear ion drift model properties. The motivation of this study is the usage of the trigonometric Blackman window function, which presents a more detailed definition and leads to more accurate results in windowing operations. The Blackman window function can address the issues of border locking and terminal state. Numerical simulations have verified this proposed structure. Additionally, the analog realizations of the memristor element constructed with the Blackman window function have been achieved on a Field Programmable Analog Array, which offers fast prototyping, serving as an alternative approach for emulating memristors.

A reconfigurable floating-gate-transistor-capacitor filter for analog signal processing

This paper introduces a fully reconfigurable floating-gate-transistor-capacitor (FGT-C) filter that exhibits compactness and power efficiency. The proposed filter incorporates a biquadratic section, enabling the generation of lowpass (LP) and bandpass (BP) outputs with adjustable filter parameters, including gains, natural frequency, quality factor, and DC levels for input and output signals. Moreover, the FGT-C filter topology demonstrates a modular structure, facilitating easy cascading and scalability of the biquadratic sections to implement high-order frequency responses. A prototype chip has been fabricated in the 0.35 μm CMOS process, where each biquadratic section occupies an area of 0.0313 mm2. The chip measurements were conducted with a supply voltage of 1.8 V and both output voltage levels programmed at 0.9 V. The biquadratic FGT-C filter exhibits a power consumption of 118.4 nW and achieves a spurious free dynamic range of 43 dB in a 10 kHz bandwidth setting. It is suitable for low-power analog signal processing in large-scale field programmable analog arrays.

A New Class of Nonlinear Resonance Networks Modeled by Levinson–Smith and Liénard Equations

We propose a new class of nonlinear resonance networks which are modeled by standard second-order nonlinear differential equations of the Levinson-Smith type or its subset, the Liénard type. In particular, we modify series and parallel RLC resonance networks such that the passive resistor in these networks is composed of a fixed part and a variable voltage-or current-controlled part. The variable resistor is then made controllable by one of the circuit’s state-space variables leading to an embedded self feedback control mechanism. A possible discrete component circuit realizing the proposed concept is presented along with its simulations and experimental verification. The filter response behavior of one of the modified series resonance circuits is also experimentally verified using a Field Programmable Analog Array.

Field Programmable Analog Array Based Non-Integer Filter Designs

The approximation of the frequency behavior of fractional-order, power-law, and double-order filters can be performed by the same rational integer-order transfer function. This can be achieved through the utilization of a curve fitting based approximation. Moreover, their implementation can be performed by the same core, by only changing the corresponding time constants and scaling factors. The aforementioned findings are experimentally verified using a Field Programmable Analog Array device.

Complex‐order controller design examples and their implementation

AbstractA systematic method for approximating the complex‐order Laplacian operator by realizable integer‐order transfer functions is presented in this work. The realization is performed by a simple structure where only one active element is used. Thanks to the employment of complex‐order impedances, both integrators and differentiators can be readily implemented by the same core simply by interchanging the associated impedance locations. The validity of the presented concept is verified through simulation and experimental results, using the OrCAD PSpice suite and a Field Programmable Analog array device.

Amplitude-Regulated Quadrature Sine-VCO Employing an OTA-C Topology

Transconductance amplifier capacitor oscillators (TACOs) readily produce phase-shifted sinusoids with low distortion over a wide frequency range. Hence, TACOs can be used in applications including telecommunications and lock-in amplifiers. The precise amplitude regulation needed in such applications necessitates an automatic gain controller (AGC) with an envelope detector. TACOs and envelope detectors have frequency-dependent nonidealities which complicate AGC design and incite amplitude modulation outside a limited frequency range. This work presents a VCO with an AGC that uses maxima sampling to compensate for envelope detector nonidealities. The VCO, which is evaluated using a field-programmable analog array, is tunable from 30 Hz to 40 kHz and consumes ≤50 μW.

The van der Pol physical reservoir computer

The van der Pol oscillator has historical and practical significance to spiking neural networks. It was proposed as one of the first models for heart oscillations, and it has been used as the building block for spiking neural networks. Furthermore, the van der Pol oscillator is also readily implemented as an electronic circuit. For these reasons, we chose to implement the van der Pol oscillator as a physical reservoir computer (PRC) to highlight its computational ability, even when it is not in an array. The van der Pol PRC is explored using various logical tasks with numerical simulations, and a field-programmable analog array circuit for the van der Pol system is constructed to verify its use as a reservoir computer. As the van der Pol oscillator can be easily constructed with commercial-off-the-shelf circuit components, this PRC could be a viable option for computing on edge devices. We believe this is the first time that the van der Pol oscillator has been demonstrated as a PRC.

Chaos in a Pendulum Adaptive Frequency Oscillator Circuit Experiment

Adaptive oscillators can learn and encode information in dynamic, plastic states. The pendulum has recently been proposed as the base oscillator of an adaptive system. In a mechanical setup, the horizontally forced pendulum adaptive frequency oscillator seeks a resonance condition by modifying the length of the pendulum's rod. This system stores the external forcing frequency when the external amplitude is small, while it can store the resonance frequency, which is affected by the nonlinearity of the pendulum, when the external amplitude is large. Furthermore, for some frequency ranges, the pendulum adaptive frequency oscillator can exhibit chaotic motion when the amplitudes are large. This adaptive oscillator could be used as a smart vibratory energy harvester device, but this chaotic region could degrade its performance by using supplementary energy to modify the rod length. The pendulum adaptive frequency oscillator’s equations of motions are discussed, and a field-programmable analog array is used as an experimental realization of this system as an electronic circuit. Bifurcation diagrams are shown for both the numerical simulations and experiments, while period-3 motion is shown for the numerical simulations. As little work has been done on the stability of adaptive oscillators, the authors believe that this work is the first demonstration of chaos in an adaptive oscillator.

A 1 + α Order Generalized Butterworth Filter Structure and Its Field Programmable Analog Array Implementation

Fractional-order Butterworth filters of order 1 + α (0 < α < 1) can be implemented by a unified structure, using the method presented in this paper. The main offered benefit is that the cutoff frequencies of the filters are fully controllable using a very simple method and, also, various types of filters (e.g., low-pass, high-pass, band-pass, and band-stop) could be realized. Thanks to the employment of a Field Programmable Analog Array device, the implementation of the introduced method is fully reconfigurable, in the sense that various types of filter functions as well as their order are both programmable.

Field-programmable analog array (FPAA) based four-state adaptive oscillator for analog frequency analysis.

Adaptive oscillators are a subset of nonlinear oscillators that can learn and encode information in dynamic states. By appending additional states onto a classical Hopf oscillator, a four-state adaptive oscillator is created that can learn both the frequency and amplitude of an external forcing frequency. Analog circuit implementations of nonlinear differential systems are usually achieved by using operational amplifier-based integrator networks, in which redesign procedures of the system topology is time consuming. Here, an analog implementation of a four-state adaptive oscillator is presented for the first time as a field-programmable analog array (FPAA) circuit. The FPAA diagram is described, and the hardware performance is presented. This simple FPAA-based oscillator can be used as an analog frequency analyzer, as its frequency state will evolve to match the external forcing frequency. Notably, this is done without any analog-to-digital conversion or pre-processing, making it an ideal frequency analyzer for low-power and low-memory applications.

Rapid prototyping mixed-signal development kit for tactile neural computing.

Intelligent sensor systems are essential for building modern Internet of Things applications. Embedding intelligence within or near sensors provides a strong case for analog neural computing. However, rapid prototyping of analog or mixed signal spiking neural computing is a non-trivial and time-consuming task. We introduce mixed-mode neural computing arrays for near-sensor-intelligent computing implemented with Field-Programmable Analog Arrays (FPAA) and Field-Programmable Gate Arrays (FPGA). The combinations of FPAA and FPGA pipelines ensure rapid prototyping and design optimization before finalizing the on-chip implementations. The proposed approach architecture ensures a scalable neural network testing framework along with sensor integration. The experimental set up of the proposed tactile sensing system in demonstrated. The initial simulations are carried out in SPICE, and the real-time implementation is validated on FPAA and FPGA hardware.